Multilayer printed wiring boards (PWB's) are generally known. See, for example, U.S. Pat. Nos. 4,921,777, 4,897,338, 4,642,160, 4,645,733, and 3,791,858. Prior art methods of fabricating multilayer PWB's, however, are deficient in a number of respects. In particular, as related to the fabrication of multilayer printed circuits requiring high circuit densities, prior art methods are deficient in a number of respects, especially with regard to methods to accomplish vertical electrical interconnection.
There are currently a number of technology drivers for the development of improved vertical interconnection materials and processes. As the PWB industry increasingly shifts from through-hole to surface mount for components, vias are becoming nothing more than a means for vertical interconnection. In addition, the rapid growth of the portable electronics industry and its need for sophisticated, small form factor components and modules in high volume has created a requirement for novel, high density vertical interconnect techniques. In the past, the relatively small market for products with this level of sophistication has been fulfilled by ceramic and deposited thin-film technologies. These techniques do not, however, have the infrastructure, cost-effectiveness or compatibility with low cost materials to address the consumer market as effectively as the PWB industry. Conversely, conventional PWB technology cannot address the high density requirements cost-effectively or in high yield because of limitations in registration, resolution capabilities of print-and-etch technology and the short life span of drill bits less than 6 mil in diameter.
Via holes in PWB's are typically mechanically drilled and plated. In conventional PWB design they are used to provide a site of attachment and interconnection for through-hole components, to electrically interconnect the front and back sides of a double sided circuit, and to route connections from the innerlayers of a multilayer circuit board. Due to the geometries involved and the nonuniform surface of resin and exposed reinforcement, these through-hole vias are difficult to metallize relative to surface circuit traces. Drilling vias through a stacked multilayer PWB wastes valuable real estate because of the sizes of vias that can be cost-effectively drilled, the large capture pads required for high yields and the lost space on layers that do not require interconnection at all points drilled. Because of this, vertical interconnection on a layer-to-layer basis is gaining popularity in multilayer PWB fabrication. Indeed, tiny microvias are now being formed using such techniques as laser, photolithography and plasma etching. There is a need in the art for materials and technologies which enable one to fill these microvias with conductors that can reliably interconnect conventional circuit layers.
The currently available methods for making layer-to-layer vertical electrical interconnection include various strategies employing conductive polymer thick film inks, solder filling, anisotropic adhesives, electroless plating, and a number of direct metallization techniques utilizing carbon, palladium and plasma deposited seed layers. Of all these processes, only the first three are utilized to directly plug the via. All the others require an electrolytic plating step to achieve the desired barrel thickness or plug.
Polymer thick film inks (PTF's) are typically screen- or stencil-printed into vias using the techniques and concepts employed in the ceramic substrate industry. These materials offer a simple two step process of fill and cure. While PTF's afford process simplicity, high density, low cost and and low process temperature, they also suffer from poor reliability and inadequate performance, as detailed in U.S. Pat. No. 5,376,403, incorporated by reference herein in its entirety.
Solder jetting and solder paste stenciling are currently employed in via filling for select applications. Obviously, stacking balls in vias one-by-one, as required in solder jetting, is a time consuming process only applicable to very high-end applications with a limited number of vias per part. Solder paste stenciling is a much more cost-effective alternative. However, the solvents and fluxes employed for solder paste stenciling have the potential to cause serious void and corrosion problems. Both approaches also suffer from reliability concerns due to potential solder remelt in subsequent assembly operations.
Anisotropically conductive film adhesives are thermoplastic polymer films that are loaded with conductive particles at a level below the percolation threshold. During assembly, the film is placed between the bare pad metallizations and pressure is applied to entrap a conductive particle between opposing bond-pads. Although the technique is attractively simple, it presents a myriad of potential problems including cross-talk from the ultra-thin bond line (&lt;1 mil), low signal speeds and carrying capacity, fragile contacts, low thermal conductivity, potential for opens and shorts from misplaced filler particles and low chemical resistance of the thermoplastic polymer.
Electroless copper plating, the most common method for forming a seed layer on the walls of vias for subsequent electroplating, is an eight step process requiring 2-3 rinses between each step. The substrates are typically microetched with permanganate, acid cleaned, conditioned, microetched to remove conditioning agent from the outer surfaces, cleaned, catalyzed (typically with colloidal Pd-Sn), accelerated with hydrochloric acid (to expose the Pd), and finally plated. The plating solution contains a reducing agent (either formaldehyde or hypophosphite), copper salts, and a chelating agent to keep the copper salts in solution (e.g., EDTA, alkanol amines, glycolic acids, tartarates). All of the chemical processes require very stringent controls and can be adversely affected by even small levels of contaminants. Based on the process flow described herein for carrying out electroless copper plating, it can be easily discerned why metallizing vias using this technique is the lowest yield process in standard PWB manufacture. Indeed, electroless copper plating is unsurpassed in terms of both process complexity and hazardous chemical usage. The alternative methods for seed coating via walls to facillitate electroplating are generally less environmentally deleterious, but suffer from equal or greater process complexity.
An additional alternative currently available for providing a conductor for vertical interconnection is to mask all but the contact pads on the circuit layer, and electroplate to a desired pin height. This process suffers the drawback of being quite expensive. Moreover, the pins thus formed are non-compliant, resulting in deformation and piercing of upper circuit layers during lamination.
In a similar vein, integrated circuit (IC) package size has been significantly reduced by the use of area array techniques in which the input/output (I/O) pads on the bare die are connected either directly or through an interposer to the circuit board with solder columns or balls on a grid pattern. Like high density multilayer PWB's, the most efficient way to connect the bare die or its package to the redistribution circuitry is by direct vertical interconnection. Typically these types of interconnections are achieved on a joint-by-joint basis using solder, wirebonding, PTF adhesives, and the like. These joints must then be encapsulated and the spaces between them filled to achieve adequate reliability. When solder is employed, a cleaning step between these two processes may also be necessary. Both of these process steps are time consuming and not always successful. Accordingly, there exists a need in the art for a less process intensive, reliable vertical interconnection strategy for these area array type component assemblies.